Design Center


- 3


.TRAN 5ns 500ns

.PRINT TRAN V(1) D(2) V(3)

.PROBE

.END

 

dig.lib, 5.

, , , , , (, ). , .

, .out:

 

**** Generated AtoD and DtoA Interfaces ****

* Analog/Digital interface for node 1

* Moving X1.U1:IN1 from analog node 1 to new digital node 1$AtoD

X$1_AtoD1 1 1$AtoD AtoD

* Analog/Digital interface for node 3

* Moving X1.U1:OUT1 from analog node 3 to new digital node 3$DtoA

X$3_DtoA1 3$DtoA 3 DtoA

* Analog/Digital interface power supply subckt

X$DIGIFPWR 0 DIGIFPWR

 

.PRINT:

 

TIME V(1) D(2) V(3)

0.000E+00 0.000E+00 1 3.551E+00

5.000E-09 1.570E-01 1 3.551E+00

1.000E-08 3.139E-01 0 3.551E+00

1.500E-08 4.704E-01 0 3.551E+00

2.000E-08 6.264E-01 1 3.551E+00

2.500E-08 7.820E-01 1 3.551E+00

3.000E-08 9.369E-01 X 3.551E+00

3.500E-08 1.091E+00 X 3.266E+00

 

, :




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