Design Center


/ - 4


.ends

*

.model DIN74 dinput (

+ s0name="0" s0tsw=3.5ns s0rlo=7.13 s0rhi=389 ; 7ohm, 0.09v

+ s1name="1" s1tsw=5.5ns s1rlo=467 s1rhi=200 ; 140ohm, 3.5v

+ s2name="X" s2tsw=3.5ns s2rlo=42.9 s2rhi=116 ; 31.3ohm, 1.35v

+ s3name="R" s3tsw=3.5ns s3rlo=42.9 s3rhi=116 ; 31.3ohm, 1.35v

+ s4name="F" s4tsw=3.5ns s4rlo=42.9 s4rhi=116 ; 31.3ohm, 1.35v

+ s5name="Z" s5tsw=3.5ns s5rlo=200K s5rhi=200K )

 

/ , . 6.4. :

 

.subckt AtoD_STD_E A D DPWR DGND

+ params: CAPACITANCE=0

*

O0 A DGND DO74 DGTLNET=D IO_STD

C1 A DGND {CAPACITANCE=0.1pF}

D0 DGND a D74CLMP

D1 1 2 D74

D2 2 DGND D74

R1 DPWR 3 4k

Q1 1 3 A 0 Q74; DGND

.ends

.model D74 D (IS=1e-16 RS=25 CJO=2pf)

.model D74CLMP D (IS=1e-15 RS=2 CJO=2pf)

.model Q74 NPN (ISE=1e-16 ISC=4e-16 BF=49 BR=.03 CJE=1pf

+ CJC=.5pf CJS=3pf VJE=0.9v VJC=0.8v VJS=0.7v MIE=0.5

+ MJC=0.33 MJS=0.33 TF=0.2ns TR=10ns RB=50 RC=20)

 




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